1. Field of the Invention
The present invention relates generally to semiconductor devices and more particularly to electrode structures therefor. The present invention further relates to methods of manufacturing such structures.
2. Description of the Background Art
Recently, semiconductor devices have been developed with a view to increasing integration density and processing speeds according to demands for further advanced techniques. The purposes of increasing integration scales and processing speeds are in a certain aspect contradictory. It may happen that a high degree of integration scale of semiconductor devices prevents increase of a processing speed to the contrary. Therefore, techniques which can accomplish both of those purposes will be very useful.
The tendency to enhance integration density of semiconductor devices necessarily leads to microscopic sizes of semiconductor devices or microscopic structures of individual semiconductor elements of each semiconductor device. For example, Japanese Patent Laying-Open No. 16573/1986 discloses a finely reduced structure of a MOS (metal oxide semiconductor) device. FIG. 3 shows a sectional structure of a MOS FET (field effect transistor) indicated in this prior art. The MOS FET 1 shown in FIG. 3 comprises a gate electrode 4 formed of a polycrystalline silicon layer through a thin gate oxide film 3 on a surface of a silicon substrate 2. A source region 5 and a drain region 6 formed by diffusion of impurity are spaced from each other on the surface of the silicon substrate 2. A surface region of the silicon substrate 2 located between the source region 5 and the drain region 6 is a channel region of the MOS FET 1. Conductive layer portions 7 and 8 of polycrystalline silicon for electrodes are formed on the source region 5 and the drain region 6, respectively. The respective conductive layer portions 7 and 8 extend over upper surfaces of each field oxide film 9 for device isolation from the surfaces of the source region 5 and the drain region 6, respectively. The conductive layer portions 7 and 8 for electrodes on the field oxide film 9 are connected with aluminum connection layer 11 through contact holes provided in an interlayer insulating film 10.
This prior art has the below described features from a viewpoint of the fine structure.
(1) The gate electrode 4 is formed with a gate electrode width in a lower portion thereof being different from that in an upper portion. The gate electrode width in the lower portion of the electrode 4 is shorter and accordingly a channel length of the MOS FET defined by this width can be shortened. The gate electrode width in the upper portion of the electrode 4 is wider, which serves to prevent reduction of a sectional area of the gate electrode 4. As a result of preventing the reduction of the sectional area of the gate electrode 4, it is made possible to prevent increase of a connection resistance between the gate electrode 4 and external structures such as word lines.
(2) The source region 5 and the drain region 6 have contacts with the respective aluminum connection layer regions 11 on the field oxide film 9 through the conductive layer portions 7 and 8. Consequently, it is not necessary to provide space for direct contacts between the source and the drain regions 5 and 6 and the aluminum connection layer 11. Thus, the impurity diffusion areas of the source and drain regions 5 and 6 can be reduced.
Next, main steps of manufacturing of this prior art MOS FET will be described with reference to FIGS. 4A to 4C.
First, a polycrystalline silicon layer 12 and a silicon oxide film 13 are deposited on the surface of the silicon substrate 2 provided with a field oxide film 9 (as shown in FIG. 4A).
Then, using a photolithographic process and an etching process, the silicon oxide film 13 and the polycrystalline silicon layer 12 deposited on the surface of the silicon substrate 2 are etched and removed so that a channel region of the MOS FET is provided. This etching used is plasma dry etching. As a result, a surface of the channel region is exposed on the silicon substrate 2 (as shown in FIG. 4B). Plasma etching is a method of generating and removing a volatile material through a reaction between excited atoms and molecules in the ion impacted gas plasma and the polycrystalline silicon layer 12. After the polycrystalline silicon layer 12 is removed, the surface of the silicon substrate 2 is subjected to the impact of the ions in the plasma. By the ion impact, the surface of the silicon substrate 2 is made rough an damaged.
Further, a thermal oxidation process is applied to form a gate oxide film 3 on the channel region surface of the silicon substrate 2 and inner side walls of the opening of the polycrystalline silicon layer 12. After that, a heating process is applied in an atmosphere of nitrogen to diffuse the impurity contained in the polycrystalline silicon layer 12 into the silicon substrate 2, whereby a source region 5 and a drain region 6 are formed (as shown in FIG. 4C).
However, as a result of a finely reduced structure of the elements, the MOS FET having the above described structure and manufactured in the above described steps involves disadvantages as described below.
(a) Although it is necessary to decrease the junction depth of the source and the drain regions according to the scaling rule by the reduction of the structure of the devices, it becomes difficult to control formation of those regions by thermal diffusion from the polycrystalline silicon layer 12 as the junction depth decreases.
(b) The contact method in which the source and drain regions 5 and 6 in the silicon substrate 2 are in direct contact with the conductive layer portions 7 and 8 for electrodes involves formation of a natural oxide film at the respective interfaces therebetween, which causes increase in a contact resistance and obstruction to a good ohmic contact.
(c) As shown in FIG. 4B, the step of etching and removing the silicon oxide film 13 and the polycrystalline silicon layer 12 is executed by using plasma dry etching. Consequently, as described above, the surface of the silicon substrate 2 exposed at the end of etching is damaged by plasma. Such damage deteriorates characteristics of the transistor particularly because this surface region of the silicon substrate 2 functions as the channel region of the MOS FET.
Meanwhile, there is another problem caused by the miniaturization of the device structure of the transistors, namely, the problem of fluctuation of the characteristics of the transistors caused by the generation of hot carriers. When the channel length of the transistor becomes shorter, the electric field is concentrated near the drain, generating hot carriers. Part of the hot carriers enter the gate oxide film and trapped therein. The trapped carriers cause fluctuation of the threshold voltage and the degradation of the mutual conductance. A so-called LDD (lightly doped drain) structure has been known as the structure for preventing fluctuation of the characteristics of the MOS FETs caused by the hot carriers. In the LDD structure, an impurity region having the same conductivity type as the drain region but lower concentration is provided between the channel region and the drain region. The impurity region of the low concentration releases the concentration of the electric field near itself, thereby reducing generation of the hot carriers.
As described above, the LDD MOS FET is effective in suppressing fluctuation of characteristics of the transistor caused by the generation of hot carriers, and accordingly, the improvement of the interconnection structure described above as well as the improvement of the LDD MOS FET are very important in the technique of miniaturization.